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EL7534
Data Sheet July 12, 2006 FN7431.8
Monolithic 600mA Step-Down Regulator
The EL7534 is a synchronous, integrated FET 600mA stepdown regulator with internal compensation. It operates with an input voltage range from 2.5V to 5.5V, which accommodates supplies of 3.3V, 5V, or a Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider. The EL7534 features PWM mode control. The operating frequency is typically 1.5MHz. Additional features include a 100ms Power-On-Reset output, <1A shut-down current, short-circuit protection, and over-temperature protection. The EL7534 is available in the 10 Ld MSOP package, making the entire converter occupy less than 0.15 in2 of PCB area with components on one side only. Both packages are specified for operation over the full -40C to +85C temperature range.
Features
* Less than 0.15 in2 (0.97 cm2) footprint for the complete 600mA converter * Components on one side of PCB * Max height 1.1 mm MSOP10 * 100ms Power-On-Reset output (POR) * Internally-compensated voltage mode controller * Up to 94% efficiency * <1A shut-down current * Overcurrent and over-temperature protection * Pb-free plus anneal available (RoHS compliant)
Applications
* PDA and pocket PC computers * Bar code readers
Ordering Information
PART NUMBER EL7534IY EL7534IY-T7 EL7534IY-T13 EL7534IYZ (Note) EL7534IYZ-T7 (Note) PART TAPE & MARKING REEL BPAAA BPAAA BPAAA BGAAA BGAAA 7" 13" 7" 13" PACKAGE 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) PKG. DWG. # MDP0043 MDP0043 MDP0043 MDP0043 MDP0043
* Cellular phones * Portable test equipment * Li-Ion battery powered devices * Small form factor (SFP) modules
Typical Application Diagram
EL7534 TOP VIEW
VS (2.5V to 5.5V) VIN R3 100 C2 10F C3 0.1F R5 100k POR EN FB R2* 100k VO R4 100k VDD
EL7534
EL7534IYZ-T13 BGAAA (Note)
MDP0043
LX
L1 1.8H C1 10F
VO
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
R1* 124k
C4 470pF
Pinout
EL7534 (10 LD MSOP) TOP VIEW
1 SGND 2 PGND 3 LX 4 VIN 5 VDD FB 10 VO 9 POR 8 EN 7 RSI 6
RSI
R6 100k
PGND SGND
(1.8V @ 600mA)
* VO = 0.8V * (1 + R1 / R2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7534
Absolute Maximum Ratings (TA = 25C)
VIN, VDD, POR to SGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) RSI, EN, VO, FB to SGND . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mA Operating Ambient Temperature . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER DC CHARACTERISTICS VFB IFB VIN, VDD VIN,OFF VIN,ON IDD
VDD = VIN = VEN = 3.3V, C1 = C2 = 10F, L = 1.8H, VO = 1.8V, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Feedback Input Voltage Feedback Input Current Input Voltage Minimum Voltage for Shutdown Maximum Voltage for Startup Supply Current VIN falling VIN rising PWM, VIN = VDD = 5V EN = 0, VIN = VDD = 5V
790
800
810 250
mV nA V V V A A m m A C C
2.5 2 2.2 400 0.1 70 45 1.5 T rising T falling VEN, VRSI = 0V and 3.3V VDD = 3.3V VDD = 3.3V VFB rising VFB falling ISINK = 5mA 86 35 0.8 -1 145 130
5.5 2.2 2.4 500 1 100 75
RDS(ON)-PMOS
PMOS FET Resistance
VDD = 5V, wafer test only VDD = 5V, wafer test only
RDS(ON)-NMOS NMOS FET Resistance ILMAX TOT,OFF TOT,ON IEN, IRSI VEN1, VRSI1 VEN2, VRSI2 VPOR Current Limit Over-temperature Threshold Over-temperature Hysteresis EN, RSI Current EN, RSI Rising Threshold EN, RSI Falling Threshold Minimum VFB for POR, WRT Targeted VFB Value POR Voltage Drop
1 2.4
A V V
95
% %
VOLPOR
70
mV
AC CHARACTERISTICS FPWM tRSI tSS tPOR PWM Switching Frequency Minimum RSI Pulse Width Soft-start Time Power On Reset Delay Time 80 Guaranteed by design 1.4 1.5 25 650 100 120 1.75 50 MHz ns s ms
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FN7431.8 July 12, 2006
EL7534 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME SGND PGND LX VIN VDD RSI EN POR VO FB Negative supply for the controller stage Negative supply for the power stage Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage Positive supply for the power stage Power supply for the controller stage Resets POR timer Enable Power on reset open drain output Output voltage sense Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output PIN FUNCTION
Block Diagram
100 0.1F
VDD VO 10pF + CURRENT LIMIT PWM COMPENSATION VIN
124K FB 5M +
100K CLOCK 1.5MHz EN EN SOFT-START RAMP GENERATOR
+ PWM COMPARATOR CONTROL LOGIC
P-DRIVER LX 1.8H 1.8V 600mA
10F
N-DRIVER UNDERVOLTAGE LOCKOUT TEMPERATURE SENSE
10F
2.5V3.5V
+ -
BANDGAP REFERENCE SGND
PGND 100K POR PG
RSI
POR
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FN7431.8 July 12, 2006
EL7534 Performance Curves and Waveforms
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60
VIN=5V VO=3.3V EFFICIENCY (%)
100 95 90 85 80 75 70 65
VIN=3.3V VO=2.5V
VO=1.8V VO=1.2V
VO=1V
VO=1.8V
0
200 IO (mA)
400
600
60
0
200 IO (mA)
400
600
FIGURE 1. EFFICIENCY
FIGURE 2. EFFICIENCY
1.54 VIN=5V, IO=600mA 1.52 1.5
0.1% VIN=3.3V, IO=600mA VIN=5V, IO=0A VO CHANGES 0.0% -0.1% -0.2% -0.3% -0.4% -0.5% 0 50 TA (C) 100 150 0 0.2 0.4 IO (A) 0.6 0.8 1 VIN=5V VIN=3.3V
FS (MHz)
VIN=3.3V, IO=0A 1.48 1.46 1.44 1.42 -50
FIGURE 3. FS vs JUNCTION TEMPERATURE
FIGURE 4. LOAD REGULATIONS
0.1% 0.0% -0.1% VO CHANGES -0.2% -0.3% -0.4% -0.5% -0.6% -0.7% -50 VIN=3.3V IO=600mA IIN (mA) VIN=3.3V IO=0A VIN=5V IO=0A
12 10 8 6 4 2 VIN=5V IO=600mA 0 50 TJ (C) 100 150 0 2.5 3 3.5 VIN (V) 4 4.5 5
FIGURE 5. LOAD/LINE REGULATIONS vs JUNCTION TEMPERATURE
FIGURE 6. NO LOAD INPUT CURRENT
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FN7431.8 July 12, 2006
EL7534 Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
VIN (1V/DIV) VIN (2V/DIV)
IIN (0.5A/DIV)
VO (2V/DIV) POR (2V/DIV)
VO (1V/DIV)
0.5ms/DIV
50ms/DIV
FIGURE 7. START-UP 1
FIGURE 8. START-UP 2
VIN (2V/DIV) VO (2V/DIV) IO (200mA/DIV) RSI (2V/DIV) POR (2V/DIV)
VO (50mV/DIV)
50ms/DIV
50s/DIV
FIGURE 9. POR FUNCTION
FIGURE 10. TRANSIENT RESPONSE (100mA to 500mA)
VIN (100mV/DIV) iL (0.5A/DIV)
VLX (2V/DIV) VO (10mV/DIV) 1s/DIV
FIGURE 11. STEADY-STATE
5
FN7431.8 July 12, 2006
EL7534 Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
M SO
ALLOWABLE POWER DISSIPATION (W)
ALLOWABLE POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
M =1
JA
JA
P =2 06 10 C /W
SO P 15 10 C /W
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7431.8 July 12, 2006
EL7534 Applications Information
Product Description
The EL7534 is a synchronous, integrated FET 600mA stepdown regulator which operates from an input of 2.5V to 6V. The output voltage is user-adjustable with a pair of external resistors. The internally-compensated controller makes it possible to use only two ceramic capacitors and one inductor to form a complete, very small footprint 600mA DC:DC converter. Where RL is the DC resistance on the inductor and RDSON1 the PFET on-resistance, nominal 70m at room temperature with tempco of 0.2m/C. As the input voltage drops gradually close or even bellow the preset VO, the converter gets into 100% duty ratio. At this condition, the upper PFET needs some minimum turn-off time if it is turned off. This off-time is related to input/output conditions. This makes the duty ratio appears randomly and increases the output ripple somewhat until the 100% duty ratio is reached. Larger output capacitor could reduce the random-looking ripple. Users need to verify if this condition has adverse effect on overall circuit if close to 100% duty ratio is expected.
Start-Up and Shut-Down
When the EN pin is tied to VIN, and VIN reaches approximately 2.4V, the regulator begins to switch. The output voltage is gradually increased to ensure proper softstart operation. When the EN pin is connected to a logic low, the EL7534 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1A. When the EN reaches logic HI, the regulator repeats the start-up procedure, including the soft-start function.
RSI/POR Function
When powering up, the open-collector Power-On-Reset output holds low for about 100ms after VO reaches the preset voltage. When the active-HI reset signal RSI is issued, POR goes to low immediately and holds for the same period of time after RSI comes back to LOW. The output voltage is unaffected. (Please refer to the timing diagram). When the function is not used, connect RSI to ground and leave open the pull-up resister R4 at POR pin. The POR output also serves as a 100ms delayed Power Good signal when the pull-up resister R4 is installed. The RSI pin needs to be directly (or indirectly through a resister R6) connected to Ground for this to function properly.
PWM Operation
In the PWM mode, the P channel MOSFET and N channel MOSFET always operate complementary. When the PMOSFET is on and the NMOSFET off, the inductor current increases linearly. The input energy is transferred to the output and also stored in the inductor. When the P channel MOSFET is off and the N channel MOSFET on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. Hence, the average current through the inductor is the output current. Since the inductor and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to VO divided by VIN. The output LC filter has a second order effect. To maintain the stability of the converter, the overall controller must be compensated. This is done with the fixed internally compensated error amplifier and the PWM compensator. Because the compensations are fixed, the values of input and output capacitors are 10F to 22F ceramic. The inductor is nominally 1.8H, though 1.5A to 2.2H can be used.
VO RSI 100ms POR MIN 25ns 100ms
FIGURE 14. RSI & POR TIMING DIAGRAM
Output Voltage Selection
Users can set the output voltage of the converter with a resister divider, which can be chosen based on the following formula:
R 2 V O = 0.8 x 1 + ------ R 1
100% Duty Ratio Operation
EL7534 utilizes CMOS power FET's as the internal synchronous power switches. The upper switch is a PMOS and lower switch a NMOS. This not only saves a boot capacitor, it also allows 100% turn-on of the upper PFET switch, achieving VO close to VIN. The maximum achievable VO is,
V O = V IN - ( R L + R DSON1 ) x I O
Component Selection
Because of the fixed internal compensation, the component choice is relatively narrow. We recommend 10F to 22F multi-layer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5H to 2.2H inductance for the inductor.
7
FN7431.8 July 12, 2006
EL7534
The RMS current present at the input capacitor is decided by the following formula:
V O x ( V IN - V O ) I INRMS = ----------------------------------------------- x I O V IN
Thermal Shut-Down
Once the junction reaches about 145C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130C, the regulator will restart again in the same manner as EN pin connects to logic HI.
This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as:
( V IN - V O ) x V O I IL = ------------------------------------------L x V IN x f S
Thermal Performance
The EL7534 is in a fused-lead MSOP10 package. Compared with regular MSOP10 package, the fused-lead package provides lower thermal resistance. The JA is 100C/W on a 4-layer board and 125C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance.
* L is the inductance * fS the switching frequency (nominally 1.5MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 1.5A surge current that can occur during a current limit condition. In addition to decoupling capacitors and inductor value, it is important to properly size the phase-lead capacitor C4 (Refer to the Typical Application Diagram). The phase-lead capacitor creates additional phase margin in the control loop by generating a zero and a pole in the transfer function. As a general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear at lower frequency than the pole and follow the equation below:
1 f Z = ---------------------2R 2 C 4
Layout Considerations
The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: * Separate the Power Ground ( ) and Signal Ground ( connect them only at one point right at the pins );
* Place the input capacitor as close to VIN and PGND pins as possible * Make the following PC traces as small as possible: - from LX pin to L - from CO to PGND * If used, connect the trace from the FB pin to R1 and R2 as close as possible * Maximize the copper area around the PGND pin * Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7534 Application Brief.
Over a normal range of R2 (~10-100k), C4 will range from ~470-4700pF. The pole frequency cannot be set once the zero frequency is chosen as it is dictated by the ratio of R1 and R2, which is solely determined by the desired output set point. The equation below shows the pole frequency relationship:
1 f P = --------------------------------------2 ( R 1 R 2 )C 4
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point.
8
FN7431.8 July 12, 2006
EL7534 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY SYMBOL A A1 A2 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. C 6/99
E
E1
PIN #1 I.D.
b c D
B
1 (N/2)
E E1 e
e C SEATING PLANE 0.10 C N LEADS b
H
L L1 N
0.08 M C A B
NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H".
L1 A c SEE DETAIL "X"
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN7431.8 July 12, 2006

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